The present disclosure relates to time-to-digital converters which digitize phase differences between signals.
In recent years, as digital phase locked loop circuits develop, time-to-digital converters, which digitize analog temporal information, have been actively developed. A typical time-to-digital converter receives a first signal into an inverter chain having a plurality of inverter circuits coupled in series, latches the output of each inverter circuit in synchronism with a second signal, and detects the point at which the status of the inverter chain changes, thereby digitizes the phase difference between the first and the second signals. However, this configuration cannot achieve resolution equal to or lower than the delay time of each inverter circuit. Thus, the phase difference between the output of each inverter circuit and the second signal is amplified by a time difference amplifier, and the output phase difference is also digitized by another time-to-digital converter, thereby achieving resolution equal to or lower than the delay time of each inverter circuit (see, e.g., Non-Patent Document 1: M. Lee and A. A. Abidi, “A 9b, 1.25 ps Resolution Coarse-Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue,” 2007 Symposium on VLSI Circuits Digest of Technical Papers, pp. 168-169, June 2007).
In addition, a time difference amplifier circuit is known which includes two chains each having a plurality of variable delay cells, where the two chains are cross-coupled so that the output of each variable delay cell in one chain controls the gain of each variable delay cell in the other chain (see, e.g., Non-Patent Document 2: T. Nakura, S. Mandai, M. Ikeda, and K. Asada, “Time Difference Amplifier using Closed-Loop Gain Control,” 2009 Symposium on VLSI Circuits Digest of Technical Papers, pp. 208-209, June 2009).
Conventional high-resolution time-to-digital converters require a time difference amplifier and a time-to-digital converter both at the output of each inverter circuit, thereby causing the total circuit size and the power consumption to be increased.
Accordingly, there is a need for a small-sized high-resolution time-to-digital converter.